Chip Week in Review: Co-Packaged Optics, 2D Transistors, Nvidia's Next Move

AI Summary

The latest Semiconductor Engineering weekly review packs in more signal than most quarters do: Lam Research and ASE are both expanding, data centre architectures are shifting, a new co-packaged optics (CPO) initiative is taking shape, researchers solved a key interface problem for 2D transistors, and Nvidia has a new plan in motion. Add in a purpose-built L4 autonomous driving chip from Japan's Tier IV, hardware security research from USENIX, patent lawsuits, image sensors, and a programmable AI memtransistor, and you get a clear picture of an industry pouring money into capacity while racing to redesign the chip itself. For Malaysian readers, the practical story is this: packaging and test — Malaysia's stronghold — remains the industry's bottleneck, and that supports the Penang and Kulim corridor just as the National Semiconductor Strategy gets traction.

Key Takeaways

• Lam Research (chipmaking equipment) and ASE (packaging and test) expanding at the same time is a capacity signal: the industry expects AI chip demand to keep outrunning supply, and packaging — Malaysia's core strength — is where the squeeze is.
• The CPO system architecture initiative matters because it moves optical networking into the chip package itself. Data centre hardware as we know it will look different within a few product cycles, and Malaysia's fast-growing data centre sector (especially Johor) will inherit those choices.
• A 2D-transistor interface solution and a programmable AI memtransistor are laboratory-stage work, but they mark where silicon scaling is heading once traditional transistors run out of room.
• Tier IV's L4 autonomous driving chip shows automotive AI moving from generic GPUs to purpose-built silicon — relevant to Malaysia's smart mobility and smart city ambitions.
• Patent suits and hardware security research in the same week is no coincidence: as chip value concentrates, IP disputes and physical-layer attacks both intensify. Malaysian E&E suppliers need IP hygiene and secure-by-design habits now.

What Happened

Semiconductor Engineering's "Chip Industry Week In Review" covers an unusually wide set of developments this cycle. On the capacity side, Lam Research — one of the big suppliers of wafer fabrication equipment — and ASE, the world's largest provider of outsourced semiconductor assembly and test (OSAT, meaning the companies that package and test finished chips), are both expanding. Earnings reports from across the sector landed in the same window, giving the market a fresh read on demand.

On the architecture side, the review reports shifts in data centre design and a new initiative around co-packaged optics system architecture. CPO means placing optical components — the parts that move data as light between servers — directly inside the chip package rather than as separate pluggable modules. The review also flags a "new plan" from Nvidia, whose roadmap decisions ripple through the entire supply chain, from silicon wafers to server racks to power grids.

Further out on the research frontier, the review covers a 2D-transistor interface solution — work on transistors built from materials one atom thick, which the industry sees as a candidate to keep chips shrinking after silicon hits physical limits — and a programmable AI memtransistor, an experimental device combining memory and switching that could make AI hardware far more efficient. Rounding out the week: USENIX hardware security research, patent lawsuits, image sensor developments, and an L4 autonomous driving chip from Tier IV, the Japanese self-driving software firm.

Why It Matters

Three separate items — Lam expanding, ASE expanding, and data centre shifts — point at the same conclusion. The industry is still building, and the bottleneck has moved. When demand for AI chips surged, the shortage everyone talked about was advanced logic manufacturing. The current squeeze is in advanced packaging and testing: the step where a finished wafer gets sliced, wrapped, connected to a substrate, and verified. An equipment maker and an OSAT expanding simultaneously tells you both ends of that pipeline are being reinforced.

The CPO initiative is the quieter but more consequential item. AI clusters are limited less by compute than by how fast chips can talk to each other. Moving optics into the package cuts the distance and power cost of that communication. The catch: it makes the package more complex, tighter, and harder to test — which pushes more value, and more engineering work, into exactly the OSAT layer where Malaysia sits. Nvidia's new plan, whatever its specifics, will accelerate this pattern, because when Nvidia changes its architecture, every supplier downstream retools to match.

The research items are a reminder about timelines. 2D-transistor interface work and programmable memtransistors are years from production. But interface problems are the kind of unglamorous engineering that decides whether a lab idea becomes a factory product, so solving one is a genuine step. Meanwhile, Tier IV's L4 chip shows automotive AI maturing from "run models on generic hardware" to "build silicon for one job" — the same specialisation path data centres took five years ago.

What This Means for Malaysia

Malaysia is one of the world's largest centres for semiconductor back-end work — assembly, packaging, and test — anchored in Penang and Kulim. ASE, one of the two companies expanding this week, runs major operations in Penang. That is the direct connection: when global packaging capacity grows, established packaging hubs with trained workforces and ready industrial estates are natural beneficiaries. The National Semiconductor Strategy, which aims to move Malaysia up the value chain from back-end towards design and advanced packaging, aligns with where this week's news says the industry's money is going. That timing is favourable, and it is worth saying plainly: the strategy and the market are pulling in the same direction.

The second connection is Johor's data centre boom. CPO will eventually change what gets installed in those facilities and how they are engineered. Developers and corporate tenants signing ten-year commitments today should ask their vendors how CPO-ready their designs are, or they risk paying for retrofit later.

The third is talent and IP. Hardware security research (USENIX) and patent litigation appearing in the same weekly digest is a warning to Malaysian E&E suppliers: as chip value concentrates, so do legal and security risks. Firms doing design work need disciplined IP filings; firms doing test and assembly need secure-by-design processes, not just for software but for the physical supply chain.

How Your Business Can Use This

If you are in the E&E supply chain, do three things this quarter. First, map your exposure: which of your customers touch advanced packaging, optics, or automotive AI? Those are where capex is flowing. Second, open a conversation with those customers