How Close Is Fully Autonomous Chip Design? What Synopsys' CEO Signals for Malaysia

AI Summary

Not close — and the head of the world's largest chip design software firm is saying so himself. In an interview with Semiconductor Engineering, Synopsys CEO Sassine Ghazi discussed AI agents in chip design, where autonomous engineering currently hits its limits, digital twins, and the challenges facing 3D-ICs (chips built by stacking multiple dies on top of each other). The practical takeaway for Malaysian readers: AI is moving into chip design workflows as an assistant that handles specific steps under human supervision, not as a replacement for engineers. For Malaysia's semiconductor corridor in Penang and Kulim, that distinction matters — it shapes hiring, training, and where local firms can climb the value chain over the next five years.

Key Takeaways

• Fully autonomous chip design is not on the near horizon. The interview's own framing — "how close are we?" — signals an industry still working out the boundary between AI assistance and AI autonomy.
• AI agents are the new unit of automation in chip design. Instead of one AI tool solving one problem, agents chain multiple design steps together — but with engineers still in the loop.
• 3D-IC complexity is rising faster than pure automation can absorb it. Stacked-die chips introduce thermal, testing, and integration problems that still demand human engineering judgment.
• Digital twins — virtual replicas of chips or manufacturing processes — are becoming the proving ground where design changes get tested before physical silicon is committed.
• For Malaysia, the 3D-IC discussion lands closest to home: advanced packaging, where Penang and Kulim already have scale, is becoming inseparable from design decisions.

What Happened

Semiconductor Engineering, a leading industry publication, published an interview with Sassine Ghazi, CEO of Synopsys. Synopsys is one of the biggest names in electronic design automation (EDA) — the software used to design virtually every advanced chip on the planet. When the CEO of an EDA giant talks about autonomy in chip design, it carries weight because his company builds the tools the industry would use to get there.

The conversation covered four connected themes: AI agents applied to chip design, the genuine limits of autonomous engineering, digital twins, and the technical challenges of 3D-ICs. Ghazi leads the company at a moment when the entire semiconductor sector is under pressure — chips are larger, more complex, and more expensive to design than ever, while demand for compute keeps climbing.

To understand the stakes, it helps to know what chip design actually involves. A modern chip goes through specification, logic design, synthesis (converting logic into circuit elements), place-and-route (arranging those elements physically), verification (checking the design works), and signoff before fabrication. Each stage has traditionally relied on specialist engineers using EDA software. AI entered this pipeline first as point optimisation — helping with individual steps. The interview's focus on agents reflects the next question: can AI systems that plan and execute multi-step work take over entire portions of the flow?

Why It Matters

Chips are the physical foundation of the entire AI economy. Every LLM, every data centre, every smart device runs on silicon. If chip design becomes faster and cheaper through automation, the bottleneck shifts and compute supply loosens. If it does not, design capacity stays scarce and expensive — and everything built on top of AI gets pricier. That makes this a story about the supply side of AI, not just a niche engineering topic.

The second reason this matters is the honesty of the framing. Hype-driven coverage often suggests AI can already "design chips by itself." The fact that the CEO of Synopsys is publicly discussing the limits of autonomous engineering is a useful reality check from someone with full visibility into what the tools can actually do. Our read of the interview's framing: the industry is transitioning from copilots (AI suggesting next actions) to agents (AI executing multi-step tasks), but verification and final judgment remain human responsibilities — because a design error that reaches fabrication costs millions in respins and months of delay.

Third, the 3D-IC discussion points at where complexity is heading. Traditional scaling — shrinking transistors on a single die — has gotten harder and more expensive. The industry's answer is stacking multiple dies vertically: better yield on smaller pieces, mixed process technologies, and faster time to market. But stacked chips create new problems in heat dissipation, testing, and integration. More complexity means more demand for AI assistance — and simultaneously more reasons full autonomy stays out of reach. Those two forces will define the next decade of EDA.

What This Means for Malaysia

Malaysia sits in the middle of this story, whether local executives realise it or not. The country is one of the world's largest destinations for semiconductor assembly, test, and packaging, anchored by the Penang and Kulim corridors, and the national semiconductor strategy has stated ambitions to move up the value chain into design and advanced packaging. The 3D-IC theme in this interview lands directly on that ambition: when chips are built from stacked dies, the line between "packaging" and "design" disappears. Malaysia's existing strength in packaging becomes an entry point into design-adjacent work — if the local workforce gains fluency with the AI-assisted tools that make that work manageable.

The talent angle deserves attention. One implication of AI agents handling more routine design steps — this is our analysis, not a claim from the interview — is that the experience barrier to entry in chip design may lower. A Malaysian engineer in Penang who today works on test programs could, with agentic tooling, take on design verification or die-level integration tasks that previously required a decade of specialist experience. Firms that train for this early capture the shift; firms that wait will hire for it later at a premium.

The digital twin theme also maps cleanly onto Malaysian manufacturing. Virtual replicas of production lines, packaging processes, or test flows let engineers simulate changes before touching physical equipment. For capital-intensive fabs and OSAT (outsourced assembly and test) operations in Malaysia, this is a practical next step, and process data feeding those twins needs governance under PDPA and contractual confidentiality obligations. MDEC and MyDIGITAL-era skilling programmes are the natural vehicles for building this capability locally.

How Your Business Can Use This

If you run an E&E or semiconductor-services company, treat this quarter as an evaluation window. Start with a workflow audit: list every repetitive, rules-driven engineering task your team performs — test program generation, regression failure triage, layout cleanup, documentation. These are the tasks agentic tooling addresses first. Then pick one, pilot the AI features already shipping inside the commercial EDA and test software you likely already license, and measure cycle time and error rates against your baseline. Keep engineer signoff on every output. That is the deployment model the industry itself is converging on.

If you are outside the semiconductor sector, use this as a template rather than a topic. The pattern Ghazi describes — agents orchestrating existing specialist software under human supervision — transfers directly to Malaysian finance teams (agents running reconciliation across ERP systems), logistics firms (agents handling customs documentation and exception management), and manufacturers (agents monitoring quality data and proposing corrections). The lesson from chip design is the discipline: start where errors are recoverable, keep humans at signoff, and expand autonomy only where verification is solid.

The Agentic AI Angle

What would an agent in chip design actually do? Picture this workflow: a verification agent receives a failing regression run overnight. Instead of a human sifting thousands of failure logs in the morning, the agent groups the failures, traces likely root causes, proposes fixes, runs the relevant simulations, and presents an engineer with three diagnosed options — each already tested in a digital twin. The engineer approves, and the fix flows into the design. Multi-step planning, tool invocation, self-checking, human signoff. That is the mechanism, and it is the same architecture a Penang test house can apply to test-program debugging or a KL manufacturer can apply to production anomaly investigation